Design Gateway

Design Gateway

Design Gateway Co.,Ltd



Design Gateway Co., Ltd. specializes in IP cores for high performance and low resources usage solutions in data storage, networking fields on FPGA such as NVMe, SATA, TCP/IP, UDP/IP and EMAC. We also provide Application Specific IP cores (AS-IP) for the applications which require high-speed and super low latency such as Algorithm Trading, Security, data analytics and searching applications. Providing various kinds of reference design, ready for real board evaluation and experience technology background for supporting customers.

TOE100G-IP Solution


This demo application illustrates how DG’s TOE100G-IP can incorporate with Silicom’s PacketMover work as 100GbE Network Card and fully offload multiple TCP sessions by TOE100G-IP cores.


  • Silicom NIC and PacketMover framework implemented on Silicom’s fb2CGHH@KU15P Card
  • High performance and fully offload 2 TCP sessions by 2 x TOE100G-IP
  • TCP payload is transferred directly with Host Main Memory through PCIe DMA interface
  • TCP payload with PCIe DMA transfer speed up to ~12GB/s over 100GbE



  • DG’s TOE100G-IP encrypted core.
  • Reference design project file with Silicom’s PacketMover framework and
    demo application source code.
  • TOE100G-IP datasheet and reference design documents





TOE100G-IP is described in more detail here:

Silicom’s PacketMover is an FPGA framework, designed for accelerated networking applications up to 100GbE. Providing the full feature of the standard NIC and an abstraction of the hardware layer and Software API for development of custom network packet processing applications FPGA.


Figure 1: TOE100G IP & Silicom’s PacketMover Block Diagram

TOE100G-IP Core Product Specification


  • TCP/IP stack implementation
  • Support IPv4 protocol
  • Support one session per one TOE100G IP (Multisession can be implemented by using multiple TOE100G IPs)
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmitted packet size aligned to 512-bit, transmitted data bus size
  • Total amount of received data aligned to 512-bit, received data bus size
  • Simple data interface by standard FIFO interface at 512-bit data bus
  • Simple control interface by single-port RAM interface
  • 512-bit AXI4 stream to interface with 100G Ethernet MAC
  • At least 220MHz user clock frequencyTOE
  • Reference designs available on Silicom’s fb2CGHH@KU15P Card
  • Not support data fragmentation feature
  • Customized service for following features
    • Unaligned 512-bit data transferring
    • Buffer size extension by using Windows Scaling feature
    • Network parameter assignment by other methods

  Core Facts

Provided with Core
Documentation Reference design manual Demo instruction manual
Design File Formats Encrypted HDL
Instantiation Templates VHDL
Reference Designs & Application Notes Vivado Project,

See Reference Design Manual

Additional Items Demo on fb2CGHH@KU15P card
Support Provided by Design Gateway Co., Ltd.

Table 1: Example Implementation Statistics for UltraScale+ device

Family Example Device Fmax




Kintex-Ultrascale+ XCKU5P-FFVB676-2E 350 11143 9392 1958 53 Vivado2021.2


1) Actual logic resource dependent on percentage of unrelated logic

2) Block memory resources are based on 64kB Tx data buffer size and 64kB Rx data buffer size which are maximum buffer size to achieve the best performance.