TimeSync SmartNIC FPGA FB4XXVG@Z21D

General Details

Quad Port SFP28 10/25 Gigabit Xilinx FPGA Card

The TimeSync SmartNIC FPGA FB4XXVG@Z21D is a high-performance OEM hardware platform intended for hardware acceleration for mobile 4G and 5G Baseband Units or Distributed Units with four SFP28 modules. Example: supports 100MHz carriers Radio Units via 4×10/25G eCPRI/CPRI with SFP28 modules, as well as interfacing to a Grand master via SFP28 at 10/25G.

The design is set to work in ORAN LLS-C1 and C2 with the intention to be utilized with a 4G/5G IP stack interfacing at 3GPP functional split options 8 for CPRI or 7.2x for eCPRI.

The card is based on a Xilinx® Zynq UltraScale+ RFSoC FPGA, which embeds a Processor System (PS) with four 64-bit Application Processing Units (ARM Cortex-A53) and two Real-Time Processing Units (ARM Cortex-R5) along with a powerful Programmable Logic (PL) part (UltraScale+ FPGA), as well as an integrated SD-FEC block.

Key Features
  • 5G Fronthaul with FEC offload/in-line acceleration
  • IEEE-1588-2019 compliance, Synchronous Ethernet (SyncE)
  • SmartNIC with easy customer IP integration, DPDK support
Firmware configuration

The SmartNIC FPGA Design is based on the OpenNIC platform which incorporates an RTL based low latency NIC shell and Linux Kernel driver. The NIC implementation supporting up to four PCIe physical functions (PF), with each up to 256 virtual functions (VFs), and four 10/25Gbps Ethernet ports. The shell is equipped with AXI based data and control interfaces which designed to enhance easy customer IP and user logic integration.

The onboard time synchronization circuit built with a selection of high precision oscillator, onboard GNSS receiver and Microsemi’s miTimePLL timing technology, that offers a robust and field-proven synchronization Solutions for Next-Generation 5G Applications. As for the PTP SW stack you can choose from the carrier grade Microchip PTP stack, or the opensource LinuxPTP stack, both running on the embedded ARM CPUs inside the Zynq FPGA.

fb4XXVG@Z21D-blockdiagram

Key features

TimeSync SmartNIC FB4XXVG@Z21D

  • 5G Fronthaul with FEC offload/in-line acceleration
  • IEEE-1588-2019 compliance, Synchronous Ethernet (SyncE)
  • SmartNIC with easy customer IP integration, DPDK support
  • Xilinx® Zynq UltraScale+ RFSoC FPGA
  • 1 x 4GB DDR4 (with ECC) for Programmable Logic (FPGA/PL)
  • 1 x 4GB DDR4 (with ECC) for Processing System (CPU/PS)
  • 2 x 1Gb QSPI NOR Flash for primary and failsafe image booting
Specifications

Network Interface

IEEE standard
  • IEEE 1588-2019, G8273.2, G8273.4 (T-BC/T-TSC), G8262(SyncE), G8272(PRTC/T-GM)
Ports
  • Physical interface: 4 x SFP28 (Supported SFP28 and SFP+)
  • Data Rate Supported 10/25GbE per port

Host and Card Interfaces

PCI bus
  • PCIe Gen3 x8
Other
  • Micro USB for JTAG support (FPGA programming and debug) and access to BMC
  • SD card for development support on ARM CPU

Antenna Interface

SMA
  • Onboard GNSS-receiver
  • Sync Bracket for 1 PPS and 10 MHz Sync signal propagation
  • Support for encrypted FPGA bit file (optional)

Environment

Physical
  • Full Height Half length
  • Hardware compliance: RoHS, CE
Cooling
  • Passive cooling
  • Operating temperature: 0 – 55°C, 30 – 130°F
  • Operating humidity: 20 – 80%, non-condensing
Power
  • Power consumption: Max 65W

 

FPGA Design Specification

ZU21DR Resources
  • System Logic cells – 930K
  • CLB LUT – 425K
  • SDFEC -8
  • DSP Slices – 4,272
  • BRAM – 38.0Mb
  • URAM – 22.5Mb
TimeSync HW
  • 1588/SyncE PLL with configurable clock outputs: ZL30793 Microchip clock synthesizer
  • High precision oscillator: MicrosemiOX-4011-EAE-0580-20M000
  • On-board GPS: U-blox GNSS receiver
  • TSU: Xilinx10G/25G MAC+PCS/PMA, Base-R, Two Step Timestamping
  • ToD: RTL Time of Day counter with PPS HW timestamping
TimeSync SW
  • PetaLinux on PS-ARM CPU running:
  • ZLSPTP: Microchip PTP stack with G8275.1 and G8275.2 profiles
  • PTP4L: Linux PTP stack with G8275.1 and G8275.2 profiles
  • GNSS daemon
  • T-GM, T-BC, T-TSC, SyncE applications for both zlsptp and ptp4l
  • PHC2SYS: enables synchronization between host time and adapter time.
Onboard Memory
  • 1x 4GB DDR4 (with ECC) for Programmable Logic (FPGA/PL)
  • 1x 4GB DDR4 (with ECC) for Processing System (CPU/PS)
  • 2 x 1Gb QSPI NOR Flash for primary and failsafe image booting
  • EEPROM storage with access from BMC
SmartNIC
  • OpenNIC AXI-ST based RTL design supporting up to 1024 Rx/TX queues with 4 PF
  • SR-IOV Virtual Functions (up to 256 VF)
  • Silicom’s HOST-to-PS TAP/TUN channel for file transfers and PetaLinux access
  • RawCardTool for board management features: telemetry, booting, flash upgrade
  • 3rd party LDPC and Turbo Code IPs, HARQ support
DPDK
  • Supports DPDK v20.11 LTS
  • Supports driver binding to igb_uio and vfio-pci
  • Interoperability between OpenNIC Linux driver (as PF) and DPDK driver (as PF)
  • Packet processing with configurable filters on MAC addresses, EthType
  • Dynamic queue configuration
  • Device configuration through additional driver APIs, OpeNIC Linux driver.
  • 3rd party BBDEV support for LDPC IP
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