Quad Port SFP28 10/25 Gigabit Xilinx FPGA Card
The TimeSync SmartNIC FPGA FB4XXVG@Z21D is a high-performance OEM hardware platform intended for hardware acceleration for mobile 4G and 5G Baseband Units or Distributed Units with four SFP28 modules. Example: supports 100MHz carriers Radio Units via 4×10/25G eCPRI/CPRI with SFP28 modules, as well as interfacing to a Grand master via SFP28 at 10/25G.
The design is set to work in ORAN LLS-C1 and C2 with the intention to be utilized with a 4G/5G IP stack interfacing at 3GPP functional split options 8 for CPRI or 7.2x for eCPRI.
The card is based on an AMD® Zynq UltraScale+ RFSoC FPGA, which embeds a Processor System (PS) with four 64-bit Application Processing Units (ARM Cortex-A53) and two Real-Time Processing Units (ARM Cortex-R5) along with a powerful Programmable Logic (PL) part (UltraScale+ FPGA), as well as an integrated SD-FEC block.
Key Features
- 5G Fronthaul with FEC offload/in-line acceleration
- IEEE-1588-2019 compliance, Synchronous Ethernet (SyncE)
- SmartNIC with easy customer IP integration, DPDK support
Firmware configuration
The SmartNIC FPGA Design is based on the OpenNIC platform which incorporates an RTL based low latency NIC shell and Linux Kernel driver. The NIC implementation supporting up to four PCIe physical functions (PF), with each up to 256 virtual functions (VFs), and four 10/25Gbps Ethernet ports. The shell is equipped with AXI based data and control interfaces which designed to enhance easy customer IP and user logic integration.
The onboard time synchronization circuit built with a selection of high precision oscillator, onboard GNSS receiver and Microsemi’s miTimePLL timing technology, that offers a robust and field-proven synchronization Solutions for Next-Generation 5G Applications. As for the PTP SW stack you can choose from the carrier grade Microchip PTP stack, or the opensource LinuxPTP stack, both running on the embedded ARM CPUs inside the Zynq FPGA.
