The fbCAPTURE framework is a combination of FPGA firmware and a software API in C that utilizes the full potential present in a range of FPGA based network interface cards from Silicom. For wider support and ease of integration support for DPDK, PF_RING and libPCAP is included.

The fbCAPTURE cards are designed with a combination of a powerful FPGA and large amounts of high speed onboard memory to ensure zero packet loss even at line rate performance. The fbCAPTURE API is common for all the Capture cards at 1GE, 10GE, 25GE, 40GE and 100GE link speeds. This simplifies system integration greatly, as support for multiple network speeds can be achieved with the same integration efforts.

  • Same API for all Silicom capture cards
  • Support for HW accelerated DPDK, LibPCAP and PF_RING and nTop suite
  • C based API (DLL/Shared library)
  • Linux supported
  • Multi Channel Direct Memory Access streaming (DMA) to Packet Ring Buffers (PRB)
  • Up to 64 channels to host RAM
  • 255 channels for packet transmit
  • User error handlers
  • No additional SW library dependencies
  • SW development and integration tools
  • Host server traffic load balancing
  • Up to 64 channels to multiple host processes’ memory
  • Selective traffic redirection
  • Load balancing to external hosts via optical Tx interfaces, incl logical channels
  • Dual level load balancing. Hosts & CPUs
  • Duplicate packets to multiple channels
  • Distribution without CPU overhead using 2, 3, 5 and N tuple hashing or filter rules
  • Cross-probe hash fraction distribution
  • Custom hashing
  • Silicom cards for 1, 10, 25, 40 and 100 Gbit/s
    using pluggable transceiver modules (SFP, SFP+,
    sfp28/QSA28 QSFP+, QSFP28)
  • Ethernet PHY embedded in FPGA for full packet
  • PCIe Gen1, Gen2 and Gen3 support for optimal
    host throughput
  • Monitoring via SPAN port/optical taps
  • Ethernet auto-negotiation
  • Limitless Daisy Chaining of monitored optical
    fibers between cards, at full signal strength, reducing
    number tapping of points
  • Board to board interconnect for data merge and
  • Jumbo & undersized packet support
  • A wide range of inline filters can be defined and
    combined in real-time to meet a variety of filtering
    requirements on a wide range of protocol header
  • On-the-fly reconfiguration of filters
  • Filter types available include ranges, pattern
    match, fixed/dynamic offset and value, bit masks
    and value, true/false, not, hash values, compounds
    and more on e.g.:
  • Link layer:
    ARP, Tunnels (L2TP), MAC, VLAN incl. Stacked
    VLAN, MPLS, etc.
  • Internet layer:
    IPv4, Ipv6, ICMP, RIP, OSPF, ECN, etc.
  • Transport layer:
    UDP, TCP, SCTP, etc.
  • Application layer:
    GTPv1, GTPv2, SIGTRAN, GTP-U payload headers
    incl tunneled load balancing etc.
  • Optional on-wire error and undersized frames to
    processing and capture
  • Slicing rules can be applied to conserve memory
    and storage by truncating packets
  • Fixed length slicing
  • Dynamic slicing, where truncation may start at
    offset from any specified header and include user
    definable number of bytes thereafter
  • Captured packets can be enriched with descriptors
    generated by the adapter at line rate.
  • PCAP Descriptor
  • Standard Descriptor
  • Multiple Extended Descriptor
  • Multiple time formats supported
  • Zero copy PDU handling
  • Packet indexing of protocol layers
  • No protocol parsing needed for access to individual
  • Optional insertion of time alignment ticks
    (packets) in host memory buffer every 100ms/1s
  • Optimized packet transfers for batch processing
  • Packet batching based on time or batch size
  • API supplied parsing code
  • Removal of duplicated packets
  • Configurable duplication detection parameters
  • IP fragments are correlated on-the-fly and processed
    as the initial fragment of the original packet
  • Correlated fragment handling ensures that all
    related fragments are delivered to same channel
    as specified for the complete original packet
  • True representation of on-wire packets
  • Elaborated subset of RFC2819 RMON1
  • Periodic statistics for each interface
  • Counters for special purpose firmwares
  • Network counters include: number of octets, CRC
    align errors, undersize packets, oversize packets
    incl. Jumbo frames, packet size distribution &
  • Provided via API or via supplied independent
    Silicom application
  • Temperature with preset minimum, maximum
    card operating temperature
  • Optical signal level readings
  • Link status
  • HW status validation

Resources and Downloads

Scroll to Top

Request information for : fbCAPTURE

Not sure where to start? Click 'Get Help' to connect with our dedicated team. We're here to assist you with any inquiries about our FPGA cards and solutions.

Request information for: fbCAPTURE

Seraphinite AcceleratorOptimized by Seraphinite Accelerator
Turns on site high speed to be attractive for people and search engines.