Silicom Accelerated RAN Adapter

The rapid advancement of 5G technology, driven by multiuser massive MIMO and expanded frequency bands, is revolutionizing communication with significantly increased data rates (throughput) and reduced latency (Round Trip Time). However, this progress presents substantial challenges for the software powering 5G network elements.

Critical functions in the 5G physical layer, such as Forward Error Correction (FEC) using the Low-Density Parity-Check (LDPC) algorithm, demand immense processing power. Addressing these computational needs efficiently requires offloading resource-intensive tasks to dedicated hardware.

Silicom Accelerated RAN Adapter delivers a cost-effective and high-performance solution, optimizing OPEX and CAPEX for 5G deployments.

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The Solution
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Silicom Accelerated RAN Adapter is a PCIe half-height, half-length card featuring FPGA technology to provide a versatile, programmable hardware solution designed for compute-intensive 5G physical layer offload tasks.

FPGAs (Field-Programmable Gate Arrays) offer unparalleled performance and flexibility, making them ideal for rapidly evolving technologies like 5G, where in-field updates are critical to keeping up with fast-changing standards.

Hardware Features

PCIe Gen4x16: High-speed connectivity for maximum data throughput.
Low-profile form factor, single slot: Compact and efficient design for seamless integration into existing infrastructure.
<45 W power consumption: Energy-efficient, ensuring compatibility with modern data center power requirements.

Software Interface

DPDK Integration: Seamless compatibility with the Linux Foundation’s Data Plane Development Kit (DPDK), utilizing BBDev libraries and APIs for optimized processing.
Intel® FlexRAN Support: Fully integrated into the Intel® FlexRAN software reference architecture to support modern 5G network deployments.

5G NR Specifics

Silicom Accelerated RAN Adapter is engineered to meet the latest 5G NR (New Radio) standards, ensuring peak performance and compatibility. Key features include:

Full support for 3GPP 38.212v17 specification.
Compatibility with all base graph 1 and graph 2 codes.
5G physical channel measurements as per 3GPP 38.215 standards.
HARQ (Hybrid Automatic Repeat Request) buffering for robust handling of failed transmissions.
Configurable queue support for both Downlink (DL) and Uplink (UL) operations.

FEC Performance

Designed for top-tier FEC (Forward Error Correction) performance, the accelerator achieves:

Uplink (UL) FEC decoder: Processing speeds of up to 60 Gbit/s.
Downlink (DL) FEC encoder: Processing speeds of up to 100 Gbit/s.

With the Silicom Accelerated RAN Adapter, telecom providers gain access to advanced 5G physical layer offload capabilities, ensuring high performance, energy efficiency, and reduced operational complexity. This solution positions networks to meet the demands of modern 5G standards and prepare for future advancements.