FBAP4@AGF series (BlueFjord)
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FBAP4@AGF series (BlueFjord)

Compatible with Solutions:

Silicom-Eideticom Accelerated Crypto Adapter

Silicom Accelerated RAN Adapter

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Silicom’s BlueFjord FPGA SmartNIC

 

The Silicom BlueFjord FPGA SmartNIC (FBAP4@AGF series) is a high-performance OEM hardware acceleration platform designed for compute-intensive workloads in server environments, including cryptographic processing, compression, and 5G RAN FEC/LDPC.

Built on the Altera® Agilex™ 7 F-Series FPGA with a dual F-tile package, BlueFjord supports configurations featuring a Hard Processor System with four 64-bit ARM Cortex-A53 cores alongside a powerful programmable logic fabric. FPGA capacity ranges from 573K to 2,692K logic elements, enabling tailored solutions that meet a broad spectrum of application requirements.

Serving as the hardware foundation for Silicom’s Accelerated Crypto Adapter (SACA) solution, BlueFjord offers a scalable and versatile platform capable of offloading diverse crypto algorithms. Crucially, support for Elliptic Curve Cryptography (ECC) and Post Quantum Crypto acceleration (PQC) available, supporting OpenSSL 3.5. Its compact form factor and low power consumption make it an ideal choice for solutions such as the Eideticom® NoLoad. NoLoad leverages BlueFjord to offload demanding crypto/data processing tasks from the host CPU, enhanced by onboard processor cores, extending feature capabilities of the card.

BlueFjord also serves as the primary platform for Silicom’s Accelerated RAN Adapter (SARA), engineered to meet the latest 5G New Radio standards by offloading FEC/LDPC and HARQ operations in 5G mobile radio access networks, significantly reducing deployment footprint while ensuring peak performance and compatibility.

Beyond its Silicom offered applications in SACA, SARA, and Eideticom® NoLoad, Silicom provides a comprehensive board support package including development tools, drivers, and software to facilitate rapid FPGA offload design and board management, empowering customers to implement custom acceleration solutions. Each BlueFjord SmartNIC undergoes rigorous validation to guarantee reliability and scalability in large-scale deployments requiring FPGA acceleration, making it a robust and flexible platform for next-generation compute-intensive workloads.

Target Applications                                                      
  • Compute offloading
  • Crypto look-aside offloading                       
    • Post Quantum Crypto accelration
    • Symmetric and asymmetric crypto
    • Signature generation and verification
    • Bulk encryption/decryption
  • Compression offloading
  • 5G FEC/LDPC offloading   

Key features

▪ Altera® Agilex® AGF series
o Primary models are AGF014 and AGF027
o FPGAs with and without HPS are supported
▪ ½ height, ½ length PCIe card
▪ PCIe gen4: x16
▪ Option for HPS support
o HPS model FPGA
o 4GB ECC DDR4 Memory for Logic/HPS
o eMMC for FPGA HPS boot system
▪ Option: 4GB ECC DDR4 Memory for Logic
▪ Option: PCIe Gen4 x16 over MCIO x16 (124p) to 2x MCIO x8 (74p) for bifurcated MCIO connectors
▪ Designed for <75W TDP, Typical FPGA designs consume 30W-40W on AGF014

Specifications

 

Network Interface
Host ▪ PCIe Gen4 x 16, PCB gold finger edge connector
▪ Support for SMBUS/I2C/PLDM
MCIO Optional
▪ 1x MCIO 124p (x16). Connected to FPGA transceivers allowing PCIe Gen4 x16 capability via x16 to 2x x8 Y-cable or other MCIO-124p usage.
USB
  • USB C, for JTAG, HPS UART and BMC.

General Technical Specifications
FPGA Details Intel® Agilex™ F-series
▪ 2xF-Tile, Both provide PCIe Gen4 x16 Hard IP for interface to the host
▪ DDR4 Memory controllers interfacing to the FPGA fabric
▪ Platform Management Communications Interface (PMCI) module
▪ Sample models
o AGFB014, 1.4M Logic Element Fabric, Hard Processor System (HPS)
o AGFB027, 2.7M Logic Element Fabric, Hard Processor System (HPS)
o AGFA027, 2.7M Logic Element Fabric, No HPS
Configuration ▪ Configuration flash can 2 boot images for automatic fallback to factory default image
▪ Upload of FPGA configuration to flash via PCIe from host system
▪ Direct FPGA configuration via JTAG.
On-board Memory ▪ Option
o 4GB DDR4 ECC RAM, (option) (8GB can be offered)
o 4GB DDR4 ECC RAM, for HPS and Logic (option) (8GB can be offered)
o 16 GB eMMC (option for use with HPS model)
▪ 280 MB Flash memory for non-volatile storage
On-board Clock ▪ PCIe clock: 100 MHz
▪ 8 output reprogrammable clock generator
Additional Board Support ▪ On-board power and temperature sensors (via SMBus/I2C)
▪ Board status LEDs
▪ FPGA Reset via host I2C
Environment ▪ ½ height, ½ length 76mm x 167.65 mm with bracket
▪ Storage temperature: -40 – 65°C -40 – 149°F
▪ Operating temperature (card inlet): -5 – 50°C, 23 – 122°F
▪ Operating humidity: 5 – 85%
▪ Hardware compliance: RoHS, FCC, CE
Power ▪ Max 75W
▪ Power via PCI edge connector (12V only)
▪ 4 pin AUX power connector, Usage mutually exclusive with PCIe edge connector power
Manageability Features ▪ Full card BMC solution host communication via SMBus (PLDM)
▪ FPGA image remote update capability
▪ Full security implementation using MAX10 FPGA as RoT
▪ Power and temperature monitoring via SMBus/I2C
Software Support ▪ Silicom Accelerated Crypto Adaptor (SACA)
▪ Silicom Accelerated RAN Adaptor (SARA)
▪ Eideticom NoLoad solution
▪ Silicom Board Support Package

 

Ordering Information

 

Ordering P/N 

Notes 
FBAP4@AGFB27-2T0-SH AGFB027, PCIe Gen4 x16, with HPS, 2x 4GB DDR, eMMC, no MCIO
FBAP4@AGFA27-2X0-SH AGFA027, No HPS, PCIe Gen4 x16, No DDR/eMMC, no MCIO
FBAP4@AGFB27-2LM-SH AGFB027, HPS, PCIe Gen4 x16, 1xDDR4 (HPS), 16 GB eMMC, 1x MCIO connector 124 p/x16
FBAP4@AGFB27-2TM-SH AGFB027, HPS, PCIe Gen4 x16, 2xDDR4 (PL+HPS), 16 GB eMMC, 1x MCIO connector (124p/x16)
FBAP4@AGFB14-2LM-SH AGFB014, HPS, PCIe Gen4 x16, 1xDDR4 (HPS), 16 GB eMMC, 1x MCIO connector (124p/x16)

Resources and Downloads

Product Brief
Product Brief FBAP4@AGF series (BlueFjord)

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